================================================================================ Note 41.0 Device Ordering Chart for Q-bus Systems No replies FURILO::JACKSON "If you've got straight trousers, " 353 lines 13-FEB-1986 00:27 -------------------------------------------------------------------------------- +---------------+ +-----------------+ | d i g i t a l | | uNOTE # 041 | +---------------+ +-----------------+ +----------------------------------------------------+-----------------+ | Title: Device Ordering Chart for Q-bus Systems | Date: 16-Sep-85 | +----------------------------------------------------+-----------------+ | Originator: Jack Howes and Peter Kent | Page 1 of 6 | +----------------------------------------------------+-----------------+ Primary Device Ordering Determination ------------------------------------- DMA devices as well as interrupt devices on the Q-bus are position dependant. That means that the order in which devices are placed in the bus relative to the CPU determines in what order their DMA (or interrupt) requests will be serviced. The primary factor in determining the device sequencing order is the length of time that each device can wait to become bus master without error. These errors normally occur when a controller's data buffer fills to capacity before the device connected to it has finished its transfer. Generally, the cause of this is a higher priority device (or devices) transferring data over the Q-bus, and the controller that gets the error is blocked from becoming bus master. Characteristics that influence whether a device will fail in this way are: the on board buffer size that a controller/device has, the intelligence of the controller/device, and the transfer speed of the device connected to the controller. Methodology ----------- There has been an in-house test instrument developed which can detect the failure of Q-bus devices when they cannot get bus service. This measurement is the length of time a device can wait before getting a data late or device timeout error. The test instrument can be programmed to hold the Q-bus, per acquisition, for any time between 1 microsecond and 3.9 milliseconds. It runs in conjunction with the device under test. During the test process the length of time the test instrument holds the Q-bus is varied until the device under test fails. This measurement is called "latency tolerance". Holding the Q-bus for 3.9 milliseconds is equivalent to the test instrument transferring 4095 words (non-block mode DMA) per assertion of BSACK. 389 uNOTE # 041 Page 2 of 6 Secondary Device Ordering Determination --------------------------------------- The large buffer sizes and intelligence built into some of the newer controllers make them less susceptible to data late or device time out errors. These devices do not get an error waiting for the Q-bus up to 3.9 milliseconds and consequently are ordered by other criteria: 1. The type of Q-bus transfer they do (block mode, burst mode or single cycle). See MicroNote #12 for a description of Q-bus DMA transaction types. 2. If interrupted by a lower priority DMA device will they pass the Q-bus (DMG) grant signal, when they are doing a blockmode transfer. 3. The effect the ordering has on device and system performance. 4. The power consumption and/or cabling requirements of the device. Examples: --------- o A magtape advertised as a "streaming" tape drive may not stream if it is assigned a lower priority than a device that utilizes a significant amount of bus time. In this instance the tape drive will be ordered ahead of a device that it would normally follow according to its latency tolerance. o A device that consumes a substantial amount of power may have to be configured in an expander box with another power supply for practical reasons, even though this device would normally precede other devices. The following pages contain the recommendations for the order of devices on the Q-bus. Also contained in these pages are the measurements taken and the reasons for suggesting the guidelines. This ordering table is only a guideline for Q-bus system configurations, and it should be noted that a system will work satisfactorily in many other configurations as well. Additionally, customers may alter the configurations to better meet their specific application needs. The measurement process to determine the device sequence chart has been an evolving one and as such not all the devices on the chart contain the same data. The measurements on this chart were only true for the system that they were measured on. These measurements will vary from system to system dependent upon the memory type, system architecture (mapped or unmapped DMA) and the speed of each CPU's arbitrator logic. The variations in measurements that can occur between CPU's should not theoretically effect the bus placement of each device. 390 uNOTE # 041 Page 3 of 6 Table 1 lists the order in which devices should be placed in the Q-bus. Please refer to the detailed information about each device that follows the table. Table 1 ------- 1. TSV05 9 track magtape controller 2. DMV11 Microprocessor controlled DECnet communications interface 3. TQK25 Controller for 8 inch magtape drive 4. DHV11 Microprocessor controlled communications multiplexor 5. DEQNA Ethernet controller 6. TQK50 Controller for single spindle cartridge magtape 7. RLV12 Controller for 14 inch RL series disk drives 8. RQDX3 Controller for 5 1/4 inch RD/RX drives 9. KDA50 Controller for 14 inch RA series disk drives 10. RQC25 Controller for 8 inch RC25 series disk drives 11. RQDX2 Controller for 5 1/4 inch RD/RX drives 12. DRV11-WA General purpose 22 bit DMA interface Table 2 lists the transfer time and time between requests for DATI and DATO cycles and latency tolerance. All times are microseconds. 391 uNOTE # 041 Page 4 of 6 Table 2 ------- +--------+-------------+----------------+--------------+----------+ | Device | No. words | Transfer time | Time between | Latency | | | transferred | DATI | DATO | requests | tolerance| | | | | | DATI | DATO | | +--------+-------------+--------+-------+------+-------+----------+ | TSV05 | 1 word | 2.8 | 2.8 | 8.7 | 12 | +--------+-------------+--------+-------+--------------+----------+ | DMV11 | 1 word | 3.1 | 3.1 |280 @ 56 Kbits| 175 | +--------+-------------+--------+-------+--------------+----------+ | TQK25 | 4 word | 5.1 | | | | | | block mode | | | | | | +-------------+--------+-------+--------------+ 280 | | | 4 W single | | 7.25 | | | | | & burst mode| | | | | +--------+-------------+--------+-------+--------------+----------+ | DHV11 | 1 word | 2.15 | 2.15 | | 1200 | +--------+-------------+--------+-------+------+-------+----------+ | DEQNA | 16 word | 11.78 | 13.87 | 5.1 | 5.1 | = or > | | | block mode | | | | | 3900 | +--------+-------------+--------+-------+------+-------+----------+ | TQK50 | 4 word | 9.49 | 10.7 |24.35 | 20.63 | = or > | | | burst | | | | | 3900 | +--------+-------------+--------+-------+------+-------+----------+ | RLV12 | 4 word | 7.09 | 7.8 | 5.92 | 5.7 | = or > | | | burst | | | | | 3900 | +--------+-------------+--------+-------+------+-------+----------+ | RQDX3 | 16 word | 13.5 | 12.7 | 4.48 | 4.48 | = or > | | | block mode | | | | | 3900 | +--------+-------------+--------+-------+------+-------+----------+ | KDA50 | 8 word | 9.0 | 8.9 | 6.68 | 6.68 | = or > | | | block mode | | | | | 3900 | +--------+-------------+--------+-------+------+-------+----------+ | RQC25 | 2 X 8 word | 14.84 | 16.52 |15.41 | 14.41 | = or > | | | block mode | | | | | 3900 | +--------+-------------+--------+-------+------+-------+----------+ | RQDX2 | 16 word | 15.23 | 15.48 | 1.7 | 1.7 | = or > | | | block mode | | | | | 3900 | +--------+-------------+--------+-------+------+-------+----------+ |DRV11-WA| 4 word | 6.6 | 7.0 | 0.17 | 0.17 | = or > | | | burst | | | | | 3900 * | +--------+-------------+--------+-------+------+-------+----------+ * for DEC/X11 only 392 uNOTE # 041 Page 5 of 6 Additional device information ----------------------------- TSV05 ----- This device does not do 16 word block transfer so it doesn't monitor the Q-bus BDMR (DMA request line) signal. DMV11 ----- This device does not do 16 word block transfers, so it doesn't monitor the Q-bus BDMR signal. Latency Tolerance was determined while running DECNET on a uVAX-I. The following error occurred when the DMV11 was held off the bus for more than 175us: "COPYEOPENIN RMS-F-SYS, QIO Request Failed, SYSTEM-F-LINK exit". TQK25 ----- This device does not do 16 word block transfers, so it doesn't monitor the Q-bus BDMR signal. DHV11 ----- This device does not do 16 word block transfers, so it doesn't monitor the Q-bus BDMR signal. It performs DMA on output to the controller, however is interrupt driven when accepting data from the attached asynchronous lines. DEQNA ----- This device monitors Q-bus BDMR signal and passes grant when interrupted by a lower priority device. This device is placed relatively close to the CPU because it cannot quickly recover from bus latency conditions. Re-transfers over the ethernet are costly in system resources. TQK50 ----- This device does not do 16 word block transfers, so it doesn't monitor the Q-bus BDMR signal. While this tape drive has a high latency tolerance, it should be placed in front of the other devices that utilize a significant amount of bus time. Doing this enhances its ability to stream data. 393 uNOTE # 041 Page 6 of 6 RLV12 ----- This device does not do 16 word block transfers so it doesn't monitor the Q-bus "BDMR" signal. It is configured in this position because of its ability to avoid bus latency conditions even though it doesn't do block mode transfers. RQDX3 ----- This device monitors BDMR and passes grant when interrupted by a lower priority device. This device may have to be placed as the last device in the CPU box because of cabling requirements. KDA50 ----- Instead of monitoring BDMR, the KDA50 does an eight word block transfer and releases the bus between transfers to allow other devices access. Although this device works more efficiently before the RQDX2 and RC25, it may have to be configured in an expansion box due to its high power consumption. RQC25 ----- This device does not monitor BDMR. It performs two consecutive eight word block transfers, during which it will not pass the grant to a lower priority device. RQDX2 ----- This device monitors BDMR however it does not pass grant to a lower priority device when interrupted. It holds the Q-bus from a lower priority device for 288us average. In a dual expander box system this device may have to be configured in the first expansion box due to cabling requirements. DRV11-WA -------- This device does not do 16 word block transfers so it doesn't monitor the Q-bus BDMR signal. The DRV11-WA may "monopolize" the bus if traffic to/from the device is sufficiently high. The placement of this device is very dependent upon the customers application. For DEC/X11 and diagnostic testing it should be configured as the last device on the Q-bus. 394